module shift_reg_rtl(clk, rst, ser_in, ser_out);
input     clk;
input     rst;
input  ser_in;
output ser_out;

parameter LENGTH = 4;

reg [(LENGTH-1):0] shift_reg;

always @(posedge clk or posedge rst) begin
   if (rst)
      shift_reg <= {LENGTH{1'b0}};
   else
      shift_reg <= {shift_reg[(LENGTH-2):0], ser_in};
end

assign ser_out = shift_reg[LENGTH-1];

endmodule